Synchronous random access memories such as a synchronous dynamic random access memories (SDRAMs) and a synchronous graphic random access memories (SGRAMs) are designed to operate in a synchronous memory system. Thus, all input and output signals, with the exception of a clock enable signal during power down and self refresh modes, are synchronized to an active edge of a system clock.
SDRAMs offer substantial advances in dynamic memory operating performance. For example, some SDRAMs are capable of synchronously providing burst data in a burst mode at a high-speed data rate by automatically generating a column address to address a memory array of storage cells organized in rows and columns for storing data within the SDRAM. In addition, if the SDRAM includes two or more banks of memory arrays, the SDRAM preferably permits interleaving between the two or more banks to hide precharging time. SGRAMs differ from SDRAMs by providing certain column block write functions and masked write or write-per-bit functions to accommodate high-performance graphics applications
In an asynchronous DRAM, once row and column addresses are issued to the DRAM and a row address strobe signal and column address strobe signal are deactivated, the DRAM's memory is precharged and available for another access. Another row cannot be accessed in the DRAM array, however, until the previous row access is completed.
By contrast, a SDRAM requires separate commands for accessing and precharging a row of storage cells in the SDRAM memory array. Once row and column addresses are provided to a SDRAM in a SDRAM having multiple bank memory array's, a bank memory array which is accessed remains active. An internally generated row address strobe remains active and the selected row is open until a PRECHARGE command deactivates and precharges the selected row of the memory array.
In a SDRAM, a transfer operation involves performing a PRECHARGE command operation to deactivate and precharge a previously accessed bank memory array, performing an ACTIVE command operation to register the row address and activate the bank memory array to be accessed in the transfer operation, and performing the transfer READ or WRITE command to register the column address and initiate a burst cycle.
In current SDRAMs and SGRAMs, an AUTO REFRESH command is needed each time a refresh is required. During an auto refresh operation in current SDRAMs and SGRAMs, all bank memory arrays in multibank memory devices are idle. Furthermore, the user of the SDRAM or SGRAM device does not know which bank is being refreshed. Prior art SDRAM or SGRAMs typically perform auto refresh operations by toggling between the two banks during each count of the row address. For example, the auto refresh operation is performed by refreshing row 0 of bank 0, then prior to incrementing the row address, the banks are switched to refresh row 0 of bank 1. The row address that is internally generated during the auto refresh operation is then incremented to row 1 and the banks are switched so that row 1 of bank 0 is refreshed, then the banks are switched to refresh row 1 of bank 1. This alternating between banks is continued until all rows in all banks of the memory device are refreshed. There is a need for an improved auto refresh operation in SDRAMs and SGRAMs.